1. Field of the Invention
The present invention relates to a signal processing device for a solid-state imaging element;
2. Related Art
FIGS. 5A-5C show an example of operation of a typical solid-state imaging element. FIG. 5A shows a concept for combining pixel outputs in an odd number field, FIG. 5B shows a concept for combining pixel outputs in an even number field, and FIG. 5C shows the timing relationship of pixel outputs in FIG. 5A and FIG. 5B. In these FIGS., the numerals designate respectively: 50, pixel row; 51, pixel output equivalent to a top TV line in the odd number field; 52, pixel output equivalent to a final TV line in the odd number field; 53, a pixel output equivalent to a top TV line in the even number field; and 54, a pixel output equivalent to a final TV line in the even number field.
As shown in these FIGS., a method for allotting a sum of outputs of two pixels to a TV line by alternating the combination depending on the kind of field, not allotting a pixel element to every line, is called field integration mode. While in this mode the resolution in the pixel combining direction (e.g. vertical direction in the shown example) would be somewhat degraded, this method has been widely used because the integration time necessary for obtaining the same sensitivity could be reduced to 1/2 rendering an excellent time response and the saturated charge amount determined by the pixel area could be duplicated.
On the other hand, enhancing signal reading speed in the element has been a technical obstacle for raising the frame rate. For example, while in the case of an element on the commercial market equivalent to S-VHS, the number of pixels is approximately 300,000 with the reading speed of about 10 MHz, in an element of 2,000,000 pixels for Hi-Vision the reading speed would become more than 70 MHz which is barely realized by the actual CCD transference technique from a standpoint of reading speed. To cope with this problem, there is presently considered a method in which one element is divided into a plurality of pixel areas, and a plurality of output terminals are provided, such that signals in a plurality of areas divided in one frame period are read out in parallel.
FIG. 6 shows an example in which an element is divided in half horizontally. In FIG. 6, the numerals designate respectively: 60 and 61, divided upper and lower pixel regions respectively; 62 and 63, upper and lower horizontal transference sections; 64 and 65, upper and lower output circuits. In the shown embodiment, fundamentally it would be necessary to read out in time series the upper pixel region 60 and the lower pixel region 61 in one frame period. By the division, however, they could be read out timely in parallel. Therefore, in simple words, it has been realized to reduce the reading speed in inverse proportion to the number of division.
This field integration mode has excellent features such as good time response characteristics and large saturated charge amount per pixel due to the reduction to 1/2 of the integration time for one pixel. If the regional division is made on an element in the field integration mode, however, an discontinuous line would appear on a position of the screen corresponding to the divisional connecting line, since the output level of the top TV line and the final TV line in the even number field is 1/2. As a result, such element in the field integration mode could not be used for performing regional division.